For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased functionality. The drive for ever-more functionality, however, is not without issue. It has become increasingly significant to rely heavily on innovative fabrication techniques to meet the exceedingly tight tolerance requirements imposed by scaling.
Non-volatile embedded memory with pSTTM devices can enable energy and computational efficiency. However, the technical challenges of assembling a pSTTM stack to form functional devices present formidable roadblocks to commercialization of this technology today. Specifically, reducing switching current in pSTTM devices without compromising tunnel magnetoresistance (TMR) and resistance-area (RA) are some important areas of process development. As such, significant improvements are needed in pSTTM stack development that address these challenges.